1. Field of the Invention
This invention relates generally to Analog to Digital (A/D) converters and, more specifically, to a capacitor array for a Successive Approximation Register (SAR) based Analog to Digital (A/D) converter and a method therefor.
2. Description of the Prior Art
Currently in a Successive Approximation Register (SAR) based Analog to Digital (A/D) converter, an SAR is used to signal a driver circuit to activate different columns of a capacitor array. The driver circuit is presently made up of a plurality of cells wherein each cell is used to drive a respective column of the capacitor array.
Presently, the capacitor array used in the SAR based A/D converter is a binary weighted capacitor array. In order to obtain binary weighted voltage outputs, each branch drives a capacitance value of 2.sup.n C where n is an integer greater than or equal to 0, C is the value of a unit capacitor, and each branch has a different value for n. In order to avoid fringing capacitance problems and to obtain capacitor matching, each branch is comprised of a plurality of unit capacitors C (i.e., 2.sup.n C) coupled together in parallel. For larger bits of resolution, this creates a routing nightmare as well as parasitic problems since the binary weighted capacitor array will need to drive a large number of unit capacitors C. For example, for 10 bits of resolution, 1024 unit capacitors C (i.e., 2.sup.10 C) need to be driven.
Therefore, a need existed to provide an improved capacitor array for an SAR based A/D converter. The improved capacitor array must generated a binary weighted voltage output while using substantially less unit capacitors than a conventional prior art binary weighted capacitor array. The improved capacitor array will have a plurality of branches which switch at the same speed thereby increasing the overall speed of the SAR based A/D converter.